With recent ever increasing demands for a flash memory in consumer electronics and portable electronic devices, flash memory is highly marketable, and thus the market is expected to exceed that of the existing DRAM around the year 2007. On the other hand, it is continuously required for memory devices to be highly integrated and fast in write/erase time.
The down-scaling of the existing flash memory devices having under 60 nm scale gate length is in the verge of limitation. In order to increase the speed of write and read time in existing planer channel device structure, the capacitance between control gate and floating storage electrode should be increased. Also, the coupling ratio, what is called, should be increased, and to do this, the width of a floating gate should be thick in existing device structure. In this case, though the gate length of a device is reduced, the thickness of a floating gate can not be reduced because the coupling ratio should be maintained in more than 0.6. If the size of a device having thick floating gate is reduced, the capacitance between devices is increased, thereby causing a cross-talk between cells, leading to increase the distribution of threshold voltage, and thus stumbling large scale integration. Likewise, the existing devices have difficulties in down-scaling a device, improving read/write speeds, reducing cross-talk, and the like.
One method for resolving these problems is to recess the channel region. While the recess depth gets deeper and the corner region formed on the floor of the recessed channel is shaped as round, the sensitivity of threshold voltage is very high according to the doping concentration or profile of a corner region. Moreover, in these recessed devices, the variation of threshold voltage according to substrate bias is much greater than in the existing planer channel structure, and the effective channel length is increased by the channel recess. Thus, there is a disadvantage of degrading the current driving capability when the channel width becomes narrow.
The general feature of the recessed channel devices is that the channel controllability of control electrode is inferior to that of the planer channel devices. This is associated with a large substrate bias effect. The weakened channel controllability of a control electrode takes disadvantage of slowing write/erase characteristics through the control electrode.
In the double/triple-gate MOS structure, the gate wraps the channel region. In this case, the gate electrode is excellent in the channel controllability. The applicant of the present invention has first in the world proposed a body-tied double/triple-gate MOS structure (Patent Filing No.: 2002-5325(KR), JP2003-298051(JP), U.S. Ser. No. 10/358,981) and its application to a flash memory (Korean Patent Registration No.: 0420070, U.S. patent Ser. No. 10/751,860). The applicant named this structure as a bulk FinFET. In this structure, since the channel is formed at upper side and both sidewalls of active body or at both sides of active body just as it is not recessed, the channel controllability of the gate is much more excellent than that of the existing planer channel device, and thus mostly there is no substrate bias effect. However, the width of the body should be reached around ⅔ of the physical gate length in order to suppress the short channel effect. This means that a silicon body is formed with narrower width than the minimum gate length, and thereby causing a problem in a fabrication process.
In the case of attempting to improve simply the problem associated with the down-scaling of the existing flash memory device, SONOS-type flash memory or NFGM (Nano Floating Gate Memory) can be applied to solve the problem. SONOS-type flash memory device is characterized in that 2-bit can be stored in a cell. Wherein, each 1-bit can be respectively stored in source side and drain side channel because the storage node is a dielectric layer. As a precedent, there has been an attempt to store 2-bit per a cell by using SONOS in the existing planar channel device structure (B. Eitan et al., “NROM: A novel localized trapping, 2-bit nonvolatile memory cell,” IEEE Electron Devices, vol. 21, no. 11, p. 543, 2000). However, the physical length of the channel should be at least 100 nm to store 2-bit per a cell. The reason is as follow: If the channel length of a device becomes shorter, the distance between source and drain gets closer. And it is easy that the charges stored in one side spreads to another side under a certain temperature, and thereby, easily losing the memory information.
FIG. 1 shows graphs describing as an ordinary ITRS (International Technology Roadmap for Semiconductors) roadmap. 4-bit per a cell is required as a storable bit number around 2010 from 2-bit at present. Thereby, the charges that can be in source and drain sides should not influence on each other, and the easiest method to solve this problem is to make the channel length long. As shown in FIG. 1, the down-scaling of a general flash memory is underway below 100 nm since 2004, and the gate length with about 20 nm is required in 2018 or thereabouts. Especially, the gate length of SONOS technology is required to be about 170 nm in 2005 and also required to be about 140 nm in 2018. This is the reason why the gate length is required to be long enough for storing 2-bit per a cell as described above.